`timescale 1ns/100ps
module led(
     input            I_reset_n,
     input            CLK,
     output           O_led
);
	parameter T500MS = 16'd0;
	reg [15:0] R_ledcnt;            // 中间变量buffer定义为寄存器型
	reg R_led;

	assign O_led = R_led;

	always@(posedge CLK or negedge I_reset_n)
	begin 
		 if(!I_reset_n)
		 begin   
		   R_ledcnt <= 16'd0;
		   R_led <= 1'b0;
		 end 
		 else 
		 begin   
			R_ledcnt <= R_ledcnt + 26'd1; // 计数器buffer按位加1
			if(R_ledcnt == T500MS)
		  	begin
		   		R_led <= ~R_led; // led[0]-led[7]反转一次。
		        R_ledcnt <= 16'd0;
		    end
		 end
	end

endmodule